Over the course of its life, the semiconductor industry has relied upon a strategy of scaling down the feature size of integrated chip components to improve speed and functionality of integrated chips. For many years the industry continued to fabricate decreased design sizes through decreasing the wavelength of the illumination source used for lithography. In recent years however, tool vendors have been unable to decrease the wavelength of illuminations sources and developing technology nodes now have minimum feature sizes of 20% or less than the wavelength of illumination used in exposure tools. While resolution enhancement techniques, such as immersion lithography, have allowed continued scaling through the 45 nm technology node, the need to reduce design area through non-traditional innovation has become increasingly important.
As difficult as it is to produce the minimum feature size in random logic circuits, statistical random access memory (SRAM) cells have pushed for even smaller feature size and higher density, often resulting in chips with sub-minimum design rule content. They are able to do this due to the repetitive nature of SRAM designs. SRAM designs comprise the same SRAM cell repeated over and over again throughout the SRAM design area. Since the same design is printed many times on a substrate lithography tools can be tuned to print the pitches associated with SRAM cells improving tool performance specifically for those cells.
In developing technologies, further improvement of design density for SRAM cells is also planned through exploitation of the cell edges. This is done with a two mask lithography process per layer. Such methods have been avoided in random logic fabrication since they require a data partition that is restrictive and difficult to perform.